1. Field of the invention
This invention relates to a DMA controller which executes a data transfer between an external I/O device and a memory instead of a processor. In particular, this invention relates to a DMA controller which has a function to carry out a data transfer between an external I/O device and a memory within one bus cycle.
2. Description of the prior arts
Once a DMA transfer request occurs inside or outside a DMA controller, the controller acquires a bus mastership from a processor, and then, executes a data transfer between a memory and an I/O device instead of said processor.
In general, there are two processes to carry out a data transfer. One of them is to execute a memory bus cycle and an I/O bus cycle separately. This process is called a dual address transfer because memory addresses are output during memory bus cycles and I/O addresses are output during I/O bus cycles respectively. In this dual address transfer mode, data should be once stored into data registers which are placed inside the DMA controller, in order to execute a data transfer between the memory and the I/O device.
In another process, the DMA controller executes only memory bus cycles and transfers data directly between the memory and the I/O device through data buses. This process is called a single address transfer, because the DMA controller outputs only memory addresses. In this process, the access to an I/O device is executed by a DMA transfer acknowledge signal which is active during a DMA data transfer cycle. One example of a single address transfer system is shown in FIG. 24.
In the case shown in FIG. 24, the port sizes of memory 120 and I/O device 114 are different with each other. The port size of memory 120 is two bytes, and the upper byte memory 112 is connected with the upper bytes of the data bus, while the lower byte memory 113 is connected with the lower bytes of the data bus. For example, an I/O device having one byte port size is connected with a processor system having a 16 bit data bus. The port size of I/O device 114 is one byte, and this device is connected with the lower part of the data bus. When a DMA transfer request occurs, DMA controller 111 activates a bus request signal, and requires a bus mastership against processor 110. Once a bus acknowledge signal is activated by processor 110, and so, the bus mastership is given to DMA controller 111, a DMA transfer starts.
Next, an operation, in which data are transferred from memory 120 to I/O device 114 in a single address transfer mode, will be described. First, DMA controller 111 executes a bus cycle (memory read cycle) to read out data from memory 120. At this aim, DMA controller 111 outputs the address of memory 120 into the address bus, and then, outputs control signals into the control bus for a memory read operation. During this bus cycle, the DMA transfer acknowledge signal for I/O device 114 is activated. Because the port size of I/O device 114 is one byte, the bus cycle taken by DMA controller 111 becomes one byte size access. In a memory read cycle for upper bytes, upper byte memory 112 outputs data into the upper bytes of the data bus. In FIG. 24, I/O device 114 is connected with the lower bytes of the data bus. Therefore, DMA controller 111 activates the bus switching signal in order to connect the upper bytes with the lower bytes of the data bus by means of bus switching device 115. As a result, the output data from upper byte memory 112 can be output into the lower bytes of the data bus. During this memory read cycle, I/O device 114 reads the data in the lower bytes of the data bus, using the DMA transfer response signal and the control signal.
As described in said prior art, if the port size of memory 120 is different from that of I/O device 114 in a single address transfer mode, bus switching device 115 should be provided outside the controller. Accordingly, DMA controller 111 must output bus switching signals. In the Japanese Patent Publications NOs. Sho 58-46727 and Hei 1-20781, examples of the above mentioned prior art are described.
The device, which is disclosed in the Patent Publication NO. Sho 58-46727, provides a signal to indicate whether the size of a DMA data transfer is one byte or two bytes and another signal to indicate whether it is an upper byte transfer or lower byte transfer of one byte size, as bus switching signals. In this case, an I/O device of one byte size should be connected with the lower bytes. On the other hand, in the device disclosed in the Patent Publication NO. Hei 1-20781, a signal, which becomes active when a DMA data transfer is one byte size and also it is an upper byte transfer, as a bus switching signal.
In said single address transfer systems of the prior arts, an external switching device is required as mentioned above. In addition, the DMA controller should output bus switching signals. Moreover, the connection point of an I/O device may be fixed due to the bus switching signal, thus causing a physical restriction for the structure of a microprocessor system. In some systems, each having a wide data bus, such as a 32 bit (4-byte) or 64 bit (8-byte) data bus, I/O devices having different port sizes with each other, such as one byte, two bytes, and 4 bytes, are mixed. In such systems, lots of bus switching signals and bus switching devices are required, thus causing a difficulty for designing a micro-processor systems.